[legup-announce] LegUp 4.0 Release

Andrew Canis andrewcanis at gmail.com
Mon Aug 24 10:09:38 EDT 2015


     LegUp High-Level Synthesis Research Infrastructure -- Release 4.0
                         http://legup.eecg.utoronto.ca

We are pleased to announce the release of LegUp 4.0!

LegUp 4.0 is the result of two and a half years of development done
primarily
by graduate and undergraduate students at the University of Toronto.

Major Changes in LegUp 4.0:

 1.  Bain Syrowik and Blair Fort added support for ARM processor in the
hybrid
     flow (on the DE1-SoC board).
 2.  Jason Anderson, Jeffrey Goeders (UBC), and Andrew Canis added support
for
     generic Verilog in the pure hardware flow that can be targeted to ANY
FPGA
     vendor (e.g. Xilinx) or even ASICs.  This is enabled through the use of
     generic dividers, RAM blocks and multipliers.
 3.  Jongsok Choi added support for pthreads and OpenMP in the pure hardware
     flow.  A processor is no longer necessary in the system for the HLS of
     software threads.
 4.  Andrew Canis improved loop pipelining for loops with recurrences and
     resource constraints, as described in FPL 2014 paper (Canis et al.).
 5.  Andrew Canis added support for local and grouped RAMs.  Pointer
analysis
     is used to analyze when RAMs can be kept local to a Verilog module.
LegUp
     is also able to group multiple arrays into a single RAM in the
hardware.
 6.  Blair Fort added QSys compatibility so LegUp hybrid implementations
can be
     compiled by the latest versions of Altera Quartus II (15.0)
 7.  Bain Syrowik upgraded LegUp to LLVM 3.5, which is a recent version of
LLVM.
 8.  Yu Ting (Joy) Chen updated our device support:
     Altera Cyclone II, Cyclone IV, Cyclone V, Stratix IV, Stratix V.
 9.  Mathew Hall added custom Verilog support which gives the user the
ability
     to tell LegUp to NOT perform HLS for a given function, for which they
     intend to provide their own Verilog.
 10. Ruo Long (Lanny) Lian created a new comprehensive LegUp tutorial:
     Mandelbrot Lab.  This tutorial describes how to implement and optimize
a
     Mandelbrot set computation using high-level synthesis.


Beta features in LegUp 4.0:

 1.  Jeffrey Goeders (UBC), Nazanin Calagar, Yu Ting (Joy) Chen, and
     Hsuan (Julie) Hsiao added HLS debugging support, as described in
     FPL 2014 paper (Calagar et al., Goeders et al.).
 2.  Yu Ting (Joy) Chen and Jason Anderson added if-conversion that flattens
     the control-flow graph in certain cases, which may improve performance
and
     enable loop pipelining opportunities.
 3.  Stefan Hadjis added multi-cycling support, as described in DATE 2015
paper.


For a complete list of changes see:

  http://legup.eecg.utoronto.ca/docs/4.0/releasenotes.html

If you have questions, patches, and suggestions please email them to the
LegUp
development mailing list: legup-dev at legup.org
Or email us directly at: legup at eecg.toronto.edu

If you find a bug in LegUp, please file it in our Bugzilla.

Cheers,
Andrew Canis
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