[Legup-bugs] [Bug 63] Preform MIPS soft processor in legUp?

bugzilla-daemon at legup.org bugzilla-daemon at legup.org
Tue Aug 9 10:00:11 EDT 2011


http://legup.org/bugs/show_bug.cgi?id=63

--- Comment #4 from markkao_8 at hotmail.com  ---
What is this error when I tried to make the example in examples/sra. Have you
cross that before?

# Loading work.test_bench
# Loading work.tiger
# Loading work.GreenLED_s1_arbitrator
# Loading work.GreenLED
# Loading work.HexLED_0_avalon_slave_0_arbitrator
# Loading work.HexLED_0
# Loading work.HexLED
# Loading work.hex2leds
# Loading work.RedLED_s1_arbitrator
# Loading work.RedLED
# Loading work.data_cache_0_dCacheADDR_arbitrator
# Loading work.data_cache_0_dCacheCtrlRx_arbitrator
# Loading work.data_cache_0_dCacheDATA_arbitrator
# Loading work.data_cache_0_dCacheCtrlTx_arbitrator
# Loading work.data_cache_0_dataMaster_arbitrator
# Loading work.data_cache_0
# Loading work.Cache
# Loading work.dcacheMem
# Loading altera_mf.altsyncram
# ** Fatal: (vsim-3381) Obsolete library format for design unit. Design unit
'/home/mark/legUp/legup-1.0/tiger/hybrid/processor/tiger_cache_on_avalon/tiger_sim/verilog_libs/altera_mf.altsyncram'
#    Time: 0 ns  Iteration: 0  Instance:
/test_bench/DUT/the_data_cache_0/data_cache_0/dcacheMemIns File: ../dcacheMem.v
# FATAL ERROR while loading design
# Error loading design
Error loading design
make: *** [tigersim] Error 12

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